1. Technical Field
The present invention relates generally to peripheral component interface device and in particular to devices providing an interface between a peripheral component interface local bus and backend channels. Still more particularly, the present invention relates to testing devices which provide an interface between a peripheral component interface local bus and backend input/output channels.
2. Description of the Related Art
Multifunction peripheral component interface (PCI) input/output (I/O) devices transfer data between a PCI local bus and backend I/O channels. Multifunction PCI devices may connect the PCI local bus to a number of backend channels, which may conform to any one of a variety of I/O standards such as small computer serial interface (SCSI), Ethernet, EIDE, etc. Each backend I/O channel may conform to the same standard, or different backend channels may employ different protocols.
Normal operation of multifunction PCI devices allows data to be transferred between the PCI interface and one channel at a time. However, achieving fault grade goals on multifunction PCI devices which have identical multiple backend I/O channels requires large numbers of test vectors. Even though each backend I/O channel will be tested with the same data pattern, there is considerable overhead required to switch between each backend function. Since only one backend function can have access to the PCI bus at any given time, arbitration logic built into the PCI interface determines which backend has this control. This arbitration sequence adds additional clock cycle delays each time a backend function requests control of the PCI bus to complete a bus transaction. The test time required to test multifunction PCI devices is directly proportional to the number of test vectors which must be run, and product cost is increased with increased testing cost.
It would be desirable, therefore, to reduce the number of test vectors required for testing a multifunction PCI device. It would further be advantageous if the reduction in test vectors could be achieved with a minimal addition of test circuitry to the device.